FEE development

Silicon Drift Detectors are optimally suited for low-energy X-ray spectroscopy applications due to the small capacitance (≈0.1 pF) of their collection electrodes, which minimizes the contribution of the preamplifier series noise. The large area (>70 cm2) multi-anode linear X-ray SDDs developed by our collaboration demonstrate z very good energy resolution because of the low leakage current per anode, so opening new perspectives for all applications requiring large detection areas. As an example, SDDs have been recently proposed for the LOFT (Large Observatory for X-ray Timing) mission to perform X-ray observations of compact objects and ultra-dense matters in the space with a ~10 m2 detector composed by a system of about 2000 monolithic 71 cm2 SDDs.

VEGA: an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors

The needs of the readout Front-End Electronic (FEE) for such large area detectors require new challenging designs in terms of low noise and low power consumption.
In the figures below we present the design and the first test of VEGA, a low-noise and low-power Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear multianode Silicon Drift Detectors (SDDs).

Schematic of the charge sensitive preamplifier employed in VEGA. The preamplifier consists of a folded cascode followed by a source follower. A continuous reset is implemented by means of the MOSFET Mf.

Block diagram of the VEGA ASIC.

Block diagram of the VEGA ASIC.

Measured and simulated Equivalent Noise Charge comparison. The minimum intrinsic noise of 12 electrons r.m.s. and 10.2 electrons r.m.s. are measured and simulated at +27 °C, respectively.

Comparison between the measured intrinsic ENC (with no detector connected) and simulation results at room temperature. The minimum measured intrinsic noise is 12 electrons r.m.s. (equivalent to 104 eV FWHM) at 3.6 µs shaping time while the minimum ENC predicted by the simulation is 10.2 electrons (equivalent to 88 eV FWHM) at +27 °C. The difference between the measurement and the simulation results can be due to an additional stray capacitance at the input node, inaccuracy in the low frequency noise model of the MOSFETs and higher parallel noise.

The Figure below shows the preliminary test of the VEGA ASIC bonded to a 10 mm2 SDD irradiated with a 55Fe radiation source at −30 °C. An energy resolution of 139 eV FWHM (equivalent to the ENC of 16 electrons r.m.s.) and 187 eV FWHM is measured on the pulser line and Mn Kα line of 55Fe, respectively, at the optimum peaking time of 3.6 µs. Although the anode capacitance of this SDD is about 80 fF, smaller than that one predicted for the final detector to be read-out by VEGA (350 fF), this results can be considered representative of what VEGA ASIC can reach, considering that the required resolution for the final detector is 260 eV FWHM at 6 keV.

Preliminary test of the VEGA ASIC bonded to a 10 mm2 SDD. The energy resolution of 139 eV FWHM and 187 eV FWHM on the pulser line width and Mn Kα line of 55Fe are respectively measured.